1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a complementary (CMOS) static memory using a MOS electric field transistor.
2. Description of the Related Art
An arrangement of a conventional CMOS static memory is shown in FIG. 1. More specifically, a memory cell MC includes a flip-flop circuit constituted by pull-up high resistors R.sub.1 and R.sub.2 connected to a power source V.sub.CC and pull-down n-type MOSFETs Q.sub.1 and Q.sub.2, and transmission gate transistors Q.sub.3 and Q.sub.4 selectively controlled by a word line WL. One end of each of the transistors Q.sub.3 and Q.sub.4 is connected to the corresponding one of a pair of bit lines BL and BL, and the other end of each thereof is connected to the corresponding one of internal nodes a and b in the flip-flop circuit. The static memory includes a memory cell array constituted by two-dimensionally arranging a large number of memory cells MC in a word line WL direction and a bit line BL direction. Address input signals A.sub.0 to A.sub.n are decoded by a decoder 11. When one word line WL and one pair of bit lines BL and BL are selected, data in a memory cell MC corresponding to a predetermined address is read or written. During a data read operation, complementary data of the bit lines BL and BL is differentially amplified by a sense amplifier 12, and the resultant data is output to data input/output signal pins I/Ol to I/OM by an output circuit 13, where M is the word length of the static memory. The memory cell MC serving as a static memory is controlled by a controller 14 for receiving a chip selection signal pin CE, a read/write selection signal pin WE, an output selection signal pin OE, and an address transition detection signal .phi..sub.AT generated by the decoder 11.
A control operation of peripheral circuits of the memory cell MC will be described below. A bit line load circuit 1 constituted by normally-ON n-type MOSFETs Q.sub.5 and Q.sub.6 is used as a pull-up load for reading the bit lines BL and BL, and an output from the decoder 11 causes a word line driver 2 constituted by a p-type MOSFET Q.sub.9 and an n-type MOSFET Q.sub.10 to set the word line WL to which the selected memory cell MC belongs at high potential. The bit lines BL and BL to which the selected memory cell MC belongs are selected by a column transmission gate 3. The column transmission gate 3 is constituted by n-type MOSFETs Q.sub.7 and Q.sub.8, and is selectively controlled in response to a column selection signal CD as an output from the decoder 11. Therefore, data access of the memory cell MC is performed.
In the CMOS static memory, each of the controller 14, the decoder 11, a write circuit 15, and an output circuit 13 shown in FIG. 1 is constituted by a combination of logic circuits called CMOS push-pull logic circuits in which p- and n-type MOSFETs are complimentarily connected to each other. FIG. 2 shows an arrangement of a 2-input NAND gate. More specifically, the 2-input NAND gate includes p-type MOSFETs Q.sub.21 and Q.sub.22, and an n-type MOSFET Q.sub.23, and C=A.B. Features of the CMOS push-pull logic circuit are as follows. Since a DC feedthrough current is not supplied to the CMOS push-pull logic circuit, power consumption in a stand-by mode can be set to "0", and an output oscillates in the entire range between a power source potential V.sub.CC and a ground potential V.sub.SS. Taking the n-type MOSFET Q.sub.23 for receiving an input A as an example, since the substrate potential of the MOSFET Q.sub.23 is connected to the ground potential V.sub.SS, a difference between two potentials (V.sub.CC -V.sub.SS =V.sub.CC) is applied to both the ends of the gate oxide film of the MOSFET Q.sub.23 when the input A is set at high potential, i.e., V.sub.CC. Similarly, the potential difference V.sub.CC is applied to both ends of the gate oxide film of the p-type MOSFET.
As shown in the conventional arrangement in FIG. 1, a power source voltage of the CMOS static memory is directly supplied from the power source pad V.sub.CC. Therefore, a voltage to be applied to the power source pad, i.e., an external power source voltage V.sub.CC is applied to the gate oxide film of each of the n- and p-type MOSFETs in the corresponding circuit constituted by the push-pull logic circuit, such as the controller 14, the decoder 11, the write circuit 15, and the output circuit 13. This situation is substantially the same in the sense amplifier 12, and a maximum of a voltage V.sub.CC is applied to each MOSFET. This also applies to the peripheral circuits of the memory cell MC. Since the external power source V.sub.CC is supplied to the load high resistors R.sub.1 and R.sub.2, the voltage V.sub.CC is applied to the internal nodes a and b of the memory cell MC. Therefore, the external power source voltage V.sub.CC is applied to the gate oxide films of the pull-down n-type MOSFETs Q.sub.1 and Q.sub.2 which constitute the memory cell MC. Since the word line driver 2 includes a CMOS push-pull inverter, the external power source voltage V.sub.CC is applied to the word line WL. For this reason, the external power source voltage V.sub.CC is applied to the gate oxide films of the transmission gate transistors Q.sub.3 and Q.sub.4 in the memory cell MC. In addition, since one of the bit lines BL and BL is set at a ground potential in a write mode, the external power source voltage V.sub.CC is also applied to the gate oxide films of the n-type MOSFETs Q.sub.5 and Q.sub.6 which constitute the bit line load circuit 1, and the gate oxide films of the column transmission gate n-type MOSFETs Q.sub.7 and Q.sub.8.
Thus, in the conventional CMOS static memory, the external power source voltage V.sub.CC is directly applied to both the ends of the gate oxide films of all the MOSFETs in the peripheral circuits for performing a write/read operation for the memory cell. The thicknesses of the oxide films of the MOSFETs are all equal to each other because the films are formed by one oxidation step.
In order to realize a high-capacity and high-integration CMOS static memory, a gate length L of the MOSFET must be shortened. With this shortening in gate length, the MOSFETs must be optimized, and a subthreshold current when each transistor is OFF must be decreased. In addition, the thickness of the gate oxide film must be decreased to reduce a short-channel effect of the transistors. A.sub.n example of a silicon gate oxide film tox which is optimal with respect to the gate length L is shown in FIG. 3.
Along with a decrease in thickness of the gate oxide film tox, however, an allowable maximum voltage which can be applied is reduced in consideration of long-term reliability of the oxide film because an intensity of an electric field in the oxide film is increased with a decrease in thickness of the gate oxide film. FIG. 4 shows a relationship between the thickness of the silicon gate oxide film tox and an allowable application voltage. On the other hand, the external power source voltage V.sub.CC of the CMOS static memory is normally set to be 5V.+-.0.5V. As is understood from FIGS. 3 and 4, therefore, when a high-capacity CMOS static memory having an external power source voltage of 5 V is arranged according to a prior art using a MOSFET having a gate length of 0.6 .mu.m or less, reliability of the gate oxide film is degraded, and 10-year guarantee as a high-reliability product is impossible.
An arrangement of the conventional memory to compensate for the above disadvantage is shown in FIG. 5. A block diagram of the conventional arrangement shown in FIG. 1 is shown in FIG. 6 for reference. A difference between FIGS. 6 and 5 is as follows. In FIG. 6, the external power source voltage V.sub.CC is directly applied to the MOSFETs used in peripheral circuits 16, the memory cell MC, the word line driver 2, and the bit line load circuit 1. On the contrary, in FIG. 5, an internal power source voltage V.sub.CC, (&lt;V.sub.CC) generated from the external power source voltage V.sub.CC using a power source voltage drop circuit 17 is applied to the MOSFETs used in the peripheral circuits 16, the memory cell MC, the word line driver 2, and the bit line load circuit 1. Therefore, a voltage to be applied to the gate oxide films of the MOSFETs is a voltage V.sub.CC, lower than the external power source voltage V.sub.CC, thus improving reliability of the gate oxide film.
Since an instantaneous current consumption of the static memory normally exceeds 100 mA, however, a current capacity margin of the power source voltage drop circuit 17 must be sufficiently taken with respect to the instantaneous current consumption. When the power source voltage drop circuit 17 is constituted by MOSFETs, it is difficult to achieve a current capacity corresponding to the instantaneous current consumption of the memory. Therefore, a variation in internal power source voltage V.sub.CC, is increased, and an internal operation of the memory is undesirably unstable.
Although such a power source voltage drop circuit 17 includes a reference potential generator for controlling the internal power source voltage V.sub.CC, this generator requires a current consumption of 10 .mu.A or more in a stand-by mode. For this reason, a function which is a feature of the CMOS static memory, i.e., a current consumption of 2 .mu.A or less in the stand-by mode to allow battery back-up may be lost.
As described above, in the memory cell wherein the external power source voltage is applied to the gate of each n-type MOSFET, it is difficult to decrease the thickness of each gate oxide film and to shorten its gate length in consideration of long-term reliability of the gate oxide film, and hence realization of a high-capacity and high-integration memory has been prevented.
In order to achieve a high-capacity and high-integration memory, it may be proposed to generate a low internal power source voltage by the external power source voltage drop circuit, and to apply the resultant voltage to the entire static memory. In this case, however, it is difficult to obtain a current capacity corresponding to an instantaneous current consumption of the static memory, and a current consumption in a stand-by mode is undesirably increased.